1. Field of the Invention
The present invention relates to a semiconductor memory device such as a mass storage mask ROM.
2. Background of the Invention
As to a mask ROM (semiconductor memory) which is regarded as a semiconductor memory device of first prior art having the highest degree of integration, that of 16 megabits is mass-produced while that of 32 megabits is in a stage of completion of a sample and that of 64 megabits is still in the process of development at this stage. While a CDROM (second prior art) has been developed as a mass storage device, the CDROM is disadvantageously slow in data access speed as compared with the mask ROM. Further, a mechanism such as a motor is required in the system as a driver for the CDROM, and hence the overall system is disadvantageously increased in size. Thus, the cost for the system is increased in response, and reliability in data access itself is reduced as compared with the mask ROM if the motor or the like is deteriorated in accuracy. In view of such disadvantages, it is preferable to consider employment of the mask ROM in place of the CDROM.
FIG. 11 schematically shows a memory cell block structure of a semiconductor memory device according to the first prior art. In the semiconductor memory device of the first prior art, the interior of a memory cell array 51 is divided into a plurality of memory cell array blocks 52 to 55, in order to attain a high speed. Therefore, memory cell array block selecting circuits 56 are provided in correspondence to the respective memory cell array blocks 52 to 55. In the semiconductor memory device of at least 16 megabits according to the first prior art, further, a plurality of memory cell arrays 51 are arranged in parallel with each other and word line decoding circuits 61 are provided for the respective memory cell arrays 51 for attaining a high speed, as shown in FIG. 12.
FIG. 13 illustrates the block structure of the semiconductor memory device according to the first prior art. Referring to FIG. 13, numeral 62 denotes a word line predecoding circuit, numeral 63 denotes a bit line decoding circuit, numeral 64 denotes a bit line predecoding circuit, and numeral 65 denotes a sense circuit respectively. Further, FIG. 14 illustrates the structure of input/output pins provided in the semiconductor memory device according to the first prior art. Referring to FIG. 14, numeral 71 denotes a chip comprising the memory cell arrays 51 and peripheral circuits such as the sense circuit 65, symbols A0 to A21 denote address input pins, symbols D0 to D15 denote data output pins, symbol/OE denotes an output enable signal input pin, symbol/CE denotes a chip enable signal input pin, symbol Vcc denotes a power supply pin, and symbol GND denotes a ground connection pin respectively.
When a chip enable signal which is inputted in the chip enable signal input pin/CE goes low in operation of the semiconductor memory device according to the first prior art as shown in FIG. 15, a word line and a bit line are selected in accordance with address information which is inputted in any of the address input pins A0 to A21 as an address input signal, so that any memory cell in the memory cell arrays 51 is accessed. Data of the memory cell as accessed is outputted from any of the data output pins D0 to D15 slightly after an output enable signal which is inputted in the output enable signal input pin/OE goes low.
Properties of the mask ROM according to the first prior art and the CDROM according to the second prior art are as follows:
Although the mask ROM (first prior art) is at a high speed, the cost therefor is increased.
Although the CDROM (second prior art) is at a low cost and has mass storage, the same is at a low speed. In formation of a system, further, the overall system is increased in size. In addition, a driving system for the CDROM is at a high cost.
When employment of a mask ROM is considered as substitution for a CDROM as hereinabove described, therefore, a number of memory cell arrays 51 are required as shown in FIG. 13 for attaining a function which is equivalent to that of the CDROM, since the capacity of each memory cell array 51 is smaller as compared with the CDROM. When the mask ROM is employed in order to compensate for the disadvantages of the CDROM, therefore, the cost is increased. In order to replace the CDROM by the mask ROM, therefore, it is necessary to implement a mask ROM system semiconductor memory of a low cost. In other words, it is inevitably necessary to reduce the chip area of such a mask ROM system semiconductor memory.